1. Technical Field
A DRAM cell and a method for manufacturing the same are disclosed. More particularly, a DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed, which are suitable for electronic apparatuses such as a CD-R/W or game apparatus requiring a smaller memory capacity.
2. Description of the Related Art
Generally, a semiconductor memory device denotes a device capable of storing data and reading it when necessary. It includes various kinds of semiconductor memory devices such as a DRAM (Dynamic Random Access Memory)-based semiconductor memory, a magnetic disc, an optical disc and so on. Semiconductor memories have many advantages including compactness, high reliability, the ability to be produced at low cost and high speed operation. Thus, they are being widely used in the form of a main memory for computers, buried type memories in a microprocessor and a cash memory.
A unit cell structure of a DRAM includes a word line driven by a row address, a bit line driven by a column address, a cell transistor having a drain connected to the bit line and a gate connected to the word line and a capacitor connected to the source of the cell transistor.
The reading/writing of such a DRAM cell is as follows. When a certain word line is activated, the cell transistor connected to the corresponding word line is turned on. As voltage of the bit line is applied through the drain of the cell transistor, a charge is stored in the storage node electrode of the capacitor. At that time, as the voltage applied to the bit line, either a OV (operating voltage) or a Vdd (driving voltage) is supplied. And a fixed power voltage is supplied to the plate node electrode of the capacitor, usually half the driving voltage (Vdd).
In the case of MOS (Metal-Oxide-Silicon) capacitor used in the DRAM cell, there is an advantage over a general stacked capacitor in that a logic process can be used as it is.
FIG. 1 is a vertical sectional view showing a prior art DRAM cell structure having a MOS capacitor. Referring to FIG. 1, a vertical section structure of the DRAM cell includes a semiconductor substrate 10, a well 12, a device isolation film 14, a gate insulating film 16 deposited on the whole surface of the substrate, a gate electrode 18 of a cell transistor 3 and a plate node electrode 20 of a MOS capacitor 4 each being formed on top of the gate insulating film 16, a source/drain 24 of the cell transistor 3 formed in the substrate and a bit line 30 connected to the source/drain 24 through a contact electrode 28 of an interlayer insulating film 26.
In FIG. 1, the storage node electrode of the MOS capacitor 4 is the well 12 region located below the plate node electrode 20 and the insulator film between these electrodes 20, 12 becomes the gate insulating film 16. The gate electrode 18 of the cell transistor 3 is used as a word line.
A signal discharge of the DRAM cell of FIG. 1 is stored in the well 12, which is the storage node of the MOS capacitor 4 connected to the source of the cell transistor 3. The DRAM cell having the MOS capacitor 4 of FIG. 1 has an advantage over a stacked capacitor in that a logic process can be used as is. However, it is problematic in that data is stored in the well 12 which used as the storage node and thus a lot of leakage current results thereby reducing the refresh time.